Buses (or vectors) can be created by concatenating (combining) other wires or buses or parts of buses as in the example shown below. The concatenating operator in Verilog consists of the curly brackets while the individual parts that are combined are separated by comas. (See the assign statement in the module shown below.) module Combine (a, b, 0); input [3:03a; input (3:0); output 17:01 assign q = (a[3:11,2'511,b[2:011; endmodule For the module shown above, determine the value of the output q (in decimal) if the inputs (in decimal) are: a = 5 b = 10 (Note: the notation n'bxy means that it represents n-bits whose binary representation is xy. For example, 4'01100 means 4 bits represented by 1100, i.e., decimal value of 12.)
