Question

A microprocessor has an increment memory direct instruction, which adds 1 to the value in a memory location. The instruction has five stages: fetch opcode (four bus clock cycles), fetch operand address (three cycles), fetch operand (three cycles), add 1 to operand (three cycles), and store operand (three cycles).a. By what amount (in percent) will the duration of the instruction increase if we have to insert two bus wait states in each memory read and memory write operation?b. Repeat assuming that the increment operation takes 13 cycles instead of 3 cycles.

Answer 1

Answer:

a) 50%

b) 30.7 %

Explanation:

As microprocessor has an increment memory direct instruction, which adds 1 to the value in a memory location.

Answer 2

Based on the calculations, the duration of the instruction would increase by 50% and 30.77% respectively.

Given the following data:

• Fetch opcode = 4 bus clock cycles.

• Fetch operand address = 4 cycles.

• Fetch operand = 3 cycles.

• Add 1 to operand = 3 cycles.

• Store operand = 3 cycles.

How to determine the increase in duration.

First of all, we would determine the number of cycles when bus wait state are not inserted into each memory read and memory write operation:

$No.\;of\;cycle = 4+3+3+3+3$

Number of cycles = 16.

Next, we would determine the number of cycles when two (2) bus wait state are inserted into each memory read and memory write operation:

$No.\;of\;cycle = ([4+2]+[3+2]+[3+2]+[3+2]+3)\\\\No.\;of\;cycle = 6+5+5+5+3$

Number of cycles = 24.

For the total wait state, we have:

$Total\;wait\;state =24-16$

Total wait state = 8 clock cycle.

Now, we can calculate the increment in duration by using this formula:

$Duration \;increased = \frac{Total\;wait\;state }{No.\;of\;with\;no\;wait\;state} \times 100\\\\Duration \;increased = \frac{8 }{16} \times 100\\\\Duration \;increased = 0.5 \times 100$

Duration increased = 50%.

Assuming that the increment operation takes 13 cycles.

Similarly, we would determine the number of cycles when bus wait state are not inserted into each memory read and memory write operation:

$No.\;of\;cycle = 4+3+3+3+13$

Number of cycles = 34.

Next, we would determine the number of cycles when two (2) bus wait state are inserted into each memory read and memory write operation:

$No.\;of\;cycle = ([4+2]+[3+2]+[3+2]+[3+2]+13)\\\\No.\;of\;cycle = 6+5+5+5+13$

Number of cycles = 26.

For the total wait state, we have:

$Total\;wait\;state =34-26$

Total wait state = 8 clock cycle.

Now, we can calculate the increment in duration by using this formula:

$Duration \;increased = \frac{Total\;wait\;state }{No.\;of\;with\;no\;wait\;state} \times 100\\\\Duration \;increased = \frac{8 }{26} \times 100\\\\Duration \;increased = 0.3077 \times 100$

Duration increased = 30.77%.

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