Consider a dynamically scheduled single-issue processor that uses Tomasulo's algorithm with the following execution latencies: 3 cycles for LD (+1 cycle for address computation), 2 cycles for ADD, 4 cycles for MUL, and 5 cycles for DIV. If a program has the following instructions: LD F0, 0(R1), ADD F2, F0, F4, MUL F6, F2, F8, and DIV F10, F6, F12, how many cycles will it take to execute the program?
