Design an 8-function ALU in Verilog (in EDA Playground) that accepts 4-bit inputs a and b, a 3-bit input signal select, and produces a 5-bit output out. The ALU implements the following functions based on 3-bit input signal select.
Select Signal Function
3'b000 out = a
3'b001 out = a+b
3'b010 out = a-b
3'b011 out = a/b
3'b100 out = a %b (remainder)
3'b101 out = a << 1
3'b110 out = a >> 1
3b111 out = (a>b) (magnitude comparison)
You must simulate all these eight functions using a testbench. Test the design for (a = 3, b = 1), and (a = 2, b = 4).
