Consider the design of a CMOS compound OR-OR-AND-INVERT (OAI22) gate computing F = (A + B) middot (C + D). Estimate delay by using Logical Effort Design a transistor-level circuit Draw a stick diagram Let's say this device has transistor widths chosen to achieve effective rise and fall resistance equal to that of a unit inverter (R). and calculate diffusion capacitance Estimate the delay by using Elmore delay model
