You are asked to optimize a cache design for the given references. There are three direct-mapped cache designs possible, all with a total of 8 words of data:
C1 has 1-word blocks,
C2 has 2-word blocks, and
C3 has 4-word blocks.
In terms of miss rate, which cache design is the best?
Assume
the miss stall time is 25 cycles, and
C1 has an access time of 2 cycles,
C2 takes 3 cycles, and
C3 takes 5 cycles,
which is the best cache design?
Cache 1 (1W) Cache 2 (26) Cache 3 (46) Word Address Binary Address Tag index | hit/miss index | hit/miss index |hit/miss 0000 0011 1 MOM 180 10110100 | 22 4 43 0010 1011 5 3 2 0000 0010 0 2 191 10111111 237 88 01011000 10111110 110 23 6. M 1 M O MOM | H 1 H m 1 1 190 14 0000 1110 181 10110101 44 0010110054 M1 M 186 1011 1010 23 2 M1 M0M 253 11111101 315 2 M 1 Cache 1: miss rate = %(an integer between 0 and 100), total cycles = Cache 2: miss rate = %sip (an integer between 0 and 100), total cycles = Cache 3: miss rate = %(an integer between 0 and 100), total cycles = Cache provides the best performance. (Fill in numbers 1,2 or 3)
