Given a 10 bit address physical and 3 bit index for the cache.
A CPU produces the following sequence of read addresses in hexadecimal:
20, 04, 28, 60, 20, 04, 28, 4C, 10, 6C, 70, 10, 60, 70
Supposing that the cache is empty to begin with, and assuming an LRU replacement, determine whether each address produces a hit or a miss for each of the following caches:
(a) Direct mapped
(b) Fully associative, and
(c) Two-way set associative
