Consider an embedded computer system with 16-bit byte addressable main memory and 64 Bytes direct-mapped cache memory. The cache block size is 8 bytes. Assume that the cache is initially empty. (i) Show how the cache controller will split the memory address into different fields in order to access the cache memory. (ii) Draw a diagram of the cache organization and label the different fields in the cache memory. (iii) The CPU access the following memory locations, in that order: c88H, 774H, 79cH, COOH, 784H, c80H, 718H, c97H, 770H, 774H. All addresses are byte addresses. For each memory reference, indicate the outcome of the reference, either "hit" or "miss". (iv) What are the final contents of the cache? That is, for each cache set and each frame within a set, indicate if the frame is empty or occupied, and if occupied, indicate the tag of the main memory block that is currently present. (v) If the address 774H is currently mapped to a cache frame, what other addresses are also currently mapped to that frame?
