write Verilog design and test bench codes for a 4-bit incrementer (A circuit that adds one to a 4-bit binary) using the 4-bit adder/subtractor module provided below. Test all possible cases
The design code for the 4-bit adder/subtractor is
module halfadder (S,C,x,y);
input x,y;
output S,C;
xor U1(S,x,y);
and U2(C,x,y);
endmodule
module fulladder (S,C,x,y,cin);
input x,y,cin;
output S, C;
wire S1,D1,D2;
halfadder HA1 (S1,D1,x,y);
halfadder HA2 (S,D2,S1,cin);
or U3(C,D1,D2);endmodule
module four_bit_adder (S, C4, A, B, Cin);
input [3:0] A,B;
input Cin;
output [3:0] S;
output C4;
fulladder FA0(S[0], C1, A[0], B[0], Cin);
fulladder FA1(S[1], C2, A[1], B[1], C1);
fulladder FA2(S[2], C3, A[2], B[2], C2);
fulladder FA3(S[3], C4, A[3], B[3], C3);
endmodule
module adder_subtractor(S, C, A, B, M);
input [3:0] A,B;
input M;
output [3:0] S;
output C;
wire [3:0]N;
wire C4;
xor XOR0(N[0],B[0], M);
xor XOR1(N[1],B[1], M);
xor XOR2(N[2],B[2], M);
xor XOR3(N[3],B[3], M);
four_bit_adder FBA(S, C4, A, N, M);
endmodule
