assume the following sequence of instructions is executed on a five-stage pipelined datapath: add x5, x10, x5 ld x28, 0(x5) ld x29,8(x5) add x29, x28, x29 add x6, x10, x11 assume that the register write is done in the first half of a cycle and register read happens in the second half of a cycle. draw multiple-clock-cycle pipeline diagrams for the following cases and answer questions: a) if there is no forwarding or hazard detection, insert nops to ensure correct execution. (4 points) b) schedule the code to avoid as many nops as possible if there is no forwarding or hazard detection. what is the code sequence after scheduling? how many nops are avoided? (4 points) c) if forwarding is applied, schedule the code to avoid as many nops as possible and show forwarding path using connections between stages. (2 points)
