design a timing generator using the structure below. the unit should generate four signals to meet the following specifications: a) f1 goes low on clock pulses 2, 9, 17, 30, and 60 b) f2 goes high on clock pulses 2, 8, 15, 35, and 56 c) f3 goes low on clock pulses 1, 8, 16, 37, and 63 d) f4 goes high on clock pulses 3, 27, 39, 41, and 63 Ia goes high on dlock puses 3,27,3941, and 63 Clock MSB Binary D counter C Combinational LSB Clear 63 6465 66 67 Clear Figure P4.47: (a) Block diagram. (b) Timing diagram.
