for a direct-mapped cache design with a 64-bit address (with byte addressing), the following bits of the address are used to access the cache. tag index offset 63-13 12-5 4-0 a) what is the cache block size (in words)? (2 points) b) how many blocks does the cache have? (2 points) c) how many bits in total are required for such a cache implementation? what is the ratio of total bits required to the data storage bits? (4 points)
