What happens if both CLR' and PRE' are 0? (Hint: Look at a schematic of the output latch and determine what consequence this input condition has.) PRE' "set. input Clock R' "reset" CLRinput A.The output will reset to B.The output will set to 1.C."This is an invalid input condition, because both outputs will set to 1 ."D."Nothing will happen, because the two signals cancel each other."
