Examine the difficulty of adding a proposed ss rs1, rs2, imm (Store Sum) instruction to RISC-V. Interpretation: Mem[Reg(rs1]] = Reg[rs2]+immediate. a) Which new functional blocks (if any) do we need for this instruction? b) Which existing functional blocks (if any) require modification? c) What new signals do we need (if any) from the control unit to support this instruction? d) Modify the figure below to demonstrate an implementation of this new instruction. Add X3 Add Sum Shirt left 1 Branch MemRead Instruction [60] MomtoReg Control ALUOP MemWrite ALUSTO Reg Write Instruction (19-15) Read register 1 Read Instruction [24-20) Road data 1 register 2 Instruction (11-7) Write Road register data 2 Write data Registers Read address PC Zero ALU ALU Instruction (31-0) Instruction memory result Address Read data Ex- 29 Write Data data memory Instruction (31-0] 32 64 Imm Gen ALU control Instruction (30,14-12)
